This invention is concerned with streams of data which have been encoded into a chip stream so that a chip rate and phase of the chip stream can be derived from the encoded data, and in particular the invention relates to a method of and an apparatus for decoding such chip streams.
There are many communications systems in which data is transmitted between a transmitter and a receiver and in which the transmitter does not explicitly transmit a copy of its clock signal. The data is transmitted using a code which ensures that timing information is present in the transmitted data. Such coded data is referred to as a xe2x80x9cchip streamxe2x80x9d. In such a system, the receiver needs to recover both the data and the timing information. This has been done in the past using a phase-locked loop (PLL).
A traditional digital PLL oversamples the received chip stream using a clock having a frequency which is an integer multiple of the transmitted chip rate. As the chip rate is increased (to provide faster communication) and/or as the multiplier of the oversampling clock is increased (to provide better the operation of the PLL), the frequency of the oversampling clock can become unmanageably high. Under these circumstances, an analogue, rather than digital, PLL might be used. However, in a system comprising an analogue receiver (or transceiver) section and a digital controller section, such an analogue PLL would either need to be integrated with the receiver (or transceiver) section, occupy a special analogue support IC, or be integrated into a mixed signal controller. All of these options are more costly than integrating the PLL into the digital controller.
The present invention is concerned with the above problems and in particular with recovering data and timing information in such a way that it can be performed in a digital controller without the need for an oversampling clock, i.e. a clock having a clock rate which is many times faster than the chip rate.
In accordance with a first aspect of the present invention, there is provided a method of decoding a stream of data which has been encoded into a chip stream so that a chip rate and phase of the chip stream can be derived from the encoded data, the method comprising decoding steps of: generating a clock signal having a clock rate which is approximately equal to the chip rate (or an integer multiple thereof); passing the chip stream along a multi-stage delay line; for each clock cycle, sampling data of the chip stream at a plurality of the stages of the delay line to produce a set of oversamples; for each clock cycle, producing an estimate of a position in a respective set of the oversamples of a chip edge in the chip stream; for at least some of the clock cycles, selecting at least one of the oversamples having a position within a confined range with respect to the estimated chip edge position; and outputting the selected oversamples. Although the clock rate may be chosen to be a small integer multiple of the approximate chip rate, there is no need for this in order to perform the method. By passing the chip stream through the delay line, oversamples are obtained without the need for an oversampling clock.
In a traditional PLL, the PLL operates to adjust the clock frequency, and therefore a variable frequency oscillator is required. A PLL action may be obtained in the present invention by adjusting the estimate of the position in the oversamples of the chip edge, thus obviating the need for a variable frequency oscillator. Indeed, in the present invention, the clock rate is preferably fixed. Also, for simplicity, each selected oversample preferably has a predetermined position with respect to the estimated chip edge position.
Although the delay per stage in the delay line may be fixed and stabilised, this adds to the complexity and cost of the receiver. In the present invention, the delay per stage of the delay line need not be stabilised. To take account of manufacturing tolerances and drift in the delay per stage, for example in dependence on time, voltage and temperature, the method preferably further includes the calibration steps of: passing a signal having a known period (for example the above-mentioned clock signal) into the delay line; sampling data of the known period signal at a plurality of stages of the delay line to produce a set of calibration oversamples; estimating from the sampled data an indication of the delay per stage of the delay line; and storing the delay per stage indication. The calibration steps are preferably performed intermittently and while the decoding steps are not being performed. For example the calibration steps may be performed at power-on, when the apparatus is transmitting, and when the communications link is being turned around. Then, when receiving, the step of selecting at least one of the oversamples preferably comprises the steps of: for each clock cycle, making a first selection of some of the oversamples in dependence upon the stored delay indication; for at least some of the clock cycles, making a second selection, from the first selection of the oversamples, of said at least one of the oversamples having a predetermined position with respect to the estimated chip edge position.
As mentioned above, a PLL action may be obtained in the present invention by adjusting the estimate of the position in the oversamples of the chip edge. More particularly, the step of producing the chip edge position estimate preferably comprises the steps of: storing a chip edge position estimate; for at least some of the clock cycles, detecting any deviation of the chip edge position from the stored chip edge position estimate; and in response to such a detected deviation, adjusting the stored chip edge position estimate. For simplicity, the stored chip edge position estimate may be limited to having a predetermined range of values. In this case, special steps may be taken if the chip edge position estimate is about to be adjusted so that it is outside the range. In particular, in a preferred embodiment of the invention, if, for a clock cycle, the value of the stored chip edge position estimate needs to be adjusted past one end of its range, it is instead adjusted to the other end of its range and none of the oversamples is selected for output; and if, for a clock cycle, the value of the stored chip edge position estimate needs to be adjusted past said other end of its range, it is instead adjusted to said one end of its range and two of the oversamples are selected for output.
In accordance with a second aspect of the present invention, there is provided an apparatus arranged to perform the method of the first aspect of the invention.
In accordance with a third aspect of the present invention, there is provided an apparatus for decoding a stream of data which has been encoded into a chip stream so that a chip rate and phase of the chip stream can be derived from the encoded data, the apparatus comprising: a clock for generating a clock signal having a clock rate which is approximately equal to the chip rate or an integer multiple thereof; a multi-stage delay line for receiving the chip stream; means clocked by the clock signal for sampling data of the chip stream at each stage of the delay line toproduce a set of oversamples; means clocked by the clock signal for producing an estimate of a position in a respective set of the oversamples of a chip edge in the chip stream; means responsive to the clock signal for selecting, for at least some of the clock cycles, at least one of the oversamples having a position within a confined range with respect to the estimated chip edge position; and means for outputting the selected oversamples.
This apparatus is preferably operable to perform any one or more of the preferred features of the method of the first aspect of the invention.